1. Field of the Invention
The present invention relates to a capacitance element in a semiconductor integrated circuit, and more particularly relates to a capacitor structure in CMOS processes.
2. Description of the Prior Art
FIG. 7 is a schematic sectional view showing a capacitance element of a conventional example 1. Referring to the figure, reference numeral 1 denotes a p type semiconductor substrate; 2 denotes a buried N well region (also referred to as a bottom N well); 3 denotes a P well region; 4 denotes a n+ active region in which the concentration of an type impurity is high; 5 denotes an insulation film such as an oxide film; 6 denotes a gate electrode formed of polysilicon or the like; 7 denotes a n+ active region; 8 denotes a p+ active region; 9 denotes another n+ active region; 10 denotes another p+ active region; and 12 denotes a N well region that electrically leads out the buried N well region 2 to the upper portion. Here, xe2x80x9cn+xe2x80x9d and xe2x80x9cp+xe2x80x9d represent that the concentrations of a n type impurity and a p type impurity are high, respectively.
In addition, reference symbol A1 represents a lead wire from the n+ active region 9, and the lead wire A1 is connected with a power supply Vdd. A2 represents a lead wire from the n+ active region 7; A3 represents a lead wire from the gate electrode 6; A4 represents a lead wire from the p+ active region 8; and A5 represents a lead wire from the other p+ active region 10. The lead wire A5 is connected with the ground GND.
Further, reference symbol T1 represents one terminal that is formed by electrically connecting the lead wire A2 and the n+ active region 7, and T2 represents the other terminal that is formed by electrically connecting the lead wire A3 and the gate electrode 6. T3 and T5 each represent a ground terminal connected with the ground GND, and T4 represents a power supply terminal connected with the power supply Vdd. Additionally, C1 represents a capacitance formed between the gate electrode and the n+ active region 4 that was formed by means of n+ implantation (the high-concentration implantation of an n-type impurity or dopant), and C2 represents capacitance formed between the buried N well region 2 and the P well region located on the N well region 2.
FIG. 8 is a CV curve showing the voltage dependence of a capacitance value in the capacitance element of the conventional example 1, and the horizontal axis shows the potential of the terminal T2 to the terminal T1. As is apparent from the CV curve, the capacitance value reduces as the potential reduces from the vicinity of 0 V toward the inversion side, and shows the curve that projects downward. Such voltage dependence becomes a problem when building an analog circuit.
An example of a circuit in which the voltage dependence of the capacitance causes the accuracy deterioration of the circuit will now be shown as below. FIG. 9 is a sample holding (S/H) circuit having the simplest configuration. Referring to the figure, the circuit is composed of a switch TG and a holding capacitor CH. Vin represents an input terminal, and Vout represents an output terminal.
The operation will next be described below.
The output signal of this sample holding circuit is received by a buffer amplifier (not shown) usually having extremely high input impedance, and is sent to the following step. The switch TG is turned on during a sampling period, and thereby the analog input voltage applied to the input terminal is applied to the capacitor CH. The switch TG is turned off during a holding period, and the charge having been accumulated in the capacitor CH for the sampling period is thereby maintained. The analog voltage on hold is then output through a buffer circuit AMP having a high input impedance.
FIG. 10 shows how such a sample holding circuit operates, by use of the operation waveforms. The vertical axis shows the voltage, and the horizontal axis shows the time. Referring to the figure, Vin shows the input voltage, Vout shows the output voltage at the normal operating time, and TG shows the clock wave. TG shows the sampling period (on) and the holding period (off).
The operation at that time will next be described in a little more detail. More specifically, for the xe2x80x9cONxe2x80x9d period when the analog input is sampled into the holding capacitor, the input voltage Vin is divided by the on resistance Ztg of the switch TG and the impedance Zc formed by the capacitor CH, and thereby a voltage that is slightly different from the input voltage is applied to the capacitor CH. For the xe2x80x9cOFFxe2x80x9d(holding) period, the voltage having been applied to the capacitor CH for the sampling period is held, and the voltage is output as an averaged voltage.
As is apparent from the operation thereof, the voltage applied to the capacitor CH is distorted when the resistance of the switch TG or the capacitance of the capacitor CH has voltage dependence. The resistance of a switch usually has voltage dependence, but the influence thereof can be reduced by means of using a large switch. However, there is nothing to be done about the influence of the voltage dependence of the capacitor. It has been difficult to produce a sample holding circuit having a higher degree of accuracy than a certain level.
Referring to FIG. 10, Voutxe2x80x2 shows how the accuracy of the waveform is reduced by the voltage dependence. The actual distortion of the voltage cannot be shown in such a figure, but the distortion can be observed by means of highly accurate measurement. The figure is slightly exaggerated for purposes of illustration.
The capacitance element of a conventional example 2 will next be illustrated in FIG. 11. Referring to the figure, reference numeral 1 denotes a p type semiconductor substrate; 2 denotes a buried N well region (bottom N well); 3 denotes a P well region; 5 denotes an insulation film such as an oxide film; 6 denotes a gate electrode formed of polysilicon or the like; 8 denotes a p+ active region; 9 denotes another n+ active region; 10 denotes a lead wire from another p+ active region 8; and 12 denotes a N well region that electrically leads out the buried N well region 2 to the upper portion. Reference symbol A1 represents a lead wire from the n+ active region 9, and the lead wire A1 is connected with a power supply Vdd. A3 represents a lead wire from the gate electrode 6; A4 represents a lead wire from another p+ active region 8; and A5 represents a lead wire from the other p+ active region 10, and is connected with the ground GND.
Further, reference symbol T1 represents one terminal that is formed by electrically connecting the lead wire A4 and the p+ active region 8, and T2 represents the other terminal that is formed by electrically connecting the lead wire A3 and the gate electrode 6. T3 represents a power supply terminal, and T5 represents a ground terminal. Additionally, C1 represents capacitance formed between the gate electrode 6 and the p well region 3.
FIG. 12 is a CV curve showing the voltage dependence of a capacitance value in the capacitance element of the conventional example 2, and the horizontal axis shows the potential of the terminal T2 to the terminal T1. As is apparent from the figure, the voltage dependence appears from the vicinity of zero bias voltage also in the capacitance element of the conventional example 2 illustrated in FIG. 11 similarly to the conventional example 1 illustrated in FIG. 7. Therefore, the accuracy of the circuit is reduced by the voltage dependence of the capacitance also in this capacitance element.
In the conventional example 1 illustrated in FIG. 7, the increase of the impurity concentration in the n+ region can reduce the voltage dependence of the capacitance element. However, the voltage dependence thereof slightly remains even if the method is used. In this respect, the increasing process of the impurity concentration in the n+ region in the conventional example 2 illustrated in FIG. 11 can be performed without adding the masks. However, the voltage dependence in the conventional example 2 is usually higher than the one in the case of FIG. 7.
Since the conventional capacitance element is arranged as mentioned above, the voltage dependence thereof has been reduced, for instance, by forming the n+ active region under the gate electrode by use of dedicated masks, thereby increasing the amount of the implanted impurity in the n+ region, and forming a capacitance between the n+ active region and the gate electrode. Therefore, the number of required photomasks increases, and the processing time for the implantation of high-concentration impurity increases. As a result, there has been a drawback that the cost of manufacturing becomes large.
The present invention has been accomplished to solve the above-mentioned problem. An object of the present invention is to provide a capacitance element in which the voltage dependence of the MOS capacitance therein is canceled out, and which thereby can be used for high-precision analog circuits.
A capacitance element according to the present invention includes: a first conduction type well region formed on a second conduction type buried well region; a second conduction type active region having a high concentration of the impurity, and formed on the first conduction type well region; and a gate electrode disposed on the active region through an oxide film, wherein the second conduction type active region and the first conduction type well region that are electrically connected with each other serve as one terminal, and the gate electrode and the buried well region that are electrically connected with each other serve as the other terminal. Accordingly, according to the present invention, the voltage dependence of the capacitance element can be improved by relatively adjusting the areas of the active region and the buried well region.
A capacitance element according to the present invention includes: a first conduction type well region formed on a second conduction type buried well region; a gate electrode disposed on the first conduction type well region through an oxide film; a leading second conduction type well region formed on the buried well region, for electrically leading out the buried well region; a first conduction type active region having a high concentration of the impurity, and disposed on the leading well region; and a second conduction type active region having a high concentration of the impurity, and also disposed on the leading well region, wherein the first conduction type well region and the second conduction type active region in which the concentration of the impurity is high, which are connected with each other serve as one terminal, and the gate electrode and the first conduction type active region which are electrically connected with each other serve as the other terminal. Accordingly, according to the present invention, the voltage dependence of the capacitance element can be improved by relatively adjusting the areas of the active regions.